1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and more specifically to a bump forming method.
2. Description of Related Art
As a method of connecting a semiconductor chip and a wiring board in a semiconductor device manufacturing process, there is a method called gang bonding by which projecting electrodes (hereinafter referred to as bumps) of, for example, Au, solder, or Cu formed on the semiconductor chip and leads of the wiring board are collectively connected together. The gang bonding is also widely used in COG (Chip On Glass) in which a semiconductor chip is directly attached to a glass substrate. For the gang bonding, the following kinds of bump are used: a stud bump used in a wire bonding technique; and a mushroom bump and a straight bump used in a plating technique. The straight bump is frequently used since it is advantageous for miniaturizing.
Japanese Patent Application Publication JP-A-Heisei 3-208347, which is referred to as Patent Document 1, discloses a technique related to a straight bump forming method. The bump forming method of Patent Document 1 is characterized by first performing plating on a wafer where a resist pattern is formed with a high current density, then performing plating while gradually reducing the current density, and finally performing plating with a relatively low current density. Such a bump forming method can shorten the plating time and can also reduce the hardness of a top part of a bump.